Reconfigurable circuits such as those that include Field Programmable Gate Arrays (FPGAs) are circuits that can be programmed to execute some sort of application. Typically, reconfigurable circuits include reconfigurable logic resources, such as reconfigurable function blocks, and reconfigurable interconnect resources, such as reconfigurable connection matrices. Each of the reconfigurable function blocks typically includes reconfigurable logic cells, while each of the reconfigurable connection matrices includes reconfigurable interconnect devices (e.g., crossbar devices).
Actual programming of a reconfigurable circuit so that it can be configured in a particular manner is generally performed using a software tool suite that may be run on a computing device such as a workstation, and storing the resulting finalized configuration data into a nonvolatile storage such as a programmable read-only memory (PROM). In order to program the reconfigurable circuit, the software tool suite typically converts a high-level description of a circuit design implementing an application into finalized configuration data. The finalized configuration data will typically be a collection of bits that can be provided to the reconfigurable circuit and ready to be acted on by the reconfigurable circuit to configure itself, without further processing and/or resolution. The configuration data may be provided upon start-up of the reconfigurable circuit or upon request by the user.
FIG. 1 depicts a conventional process for configuring a conventional reconfigurable circuit and for executing an application on the resulting configured reconfigurable circuit. The process 100 begins when register transfer logic (RTL) synthesis is performed transforming a high level description (RTL description) of a circuit design implementing an application into a low level description at 102. The RTL synthesis, in brief, involves synthesis of the circuit design. The resulting low-level description includes netlists of elementary functions that execute the same global functions as the initial RTL description. Next, the elementary functions are placed and routed (place and route) at 104. In place and route, the logic resources included in the reconfigurable function blocks of the reconfigurable circuit are assigned to implement the elementary functions, and the routing of the signals between the assigned logic resources, using the connection resources (that are included in the reconfigurable connection matrices) is determined.
Following place and route, a finalization operation is performed whereby a collection of bits that can be directly read and acted on by the reconfigurable circuit to configure itself (without further processing and/or resolution) is generated at 106. This operation typically includes generation of the bitmaps of the reconfigurable connection matrices and the configuration data of the reconfigurable function blocks present in the reconfigurable circuit. Once the configuration data is generated, it is typically stored in some nonvolatile storage such as a PROM.
Upon power-up of the reconfigurable circuit or upon user request, the reconfigurable circuit is configured using the bit information stored in the nonvolatile storage, which is typically external to the reconfigurable circuit at 108. Once the reconfigurable circuit has been properly configured, the application may be executed on the configured reconfigurable circuit at 110.
At least two issues arise when a conventional process such as the one depicted in FIG. 1 is used in configuring a reconfigurable circuit. First, since the amount of finalized configuration data in bit form can be substantial, such a process 100 typically calls for a large nonvolatile storage (i.e., PROM) for storing the finalized configuration data. Second, the bit information generated by the workstation is often unable to take into account the precise characteristics of the reconfigurable circuit being configured. For example, the software tool suite may not be able to recognize defective function blocks that may be present in the reconfigurable circuit. Further, the software tool suite may not be able to take into account the varying array sizes of different reconfigurable circuits or accommodate newer arrays not recognized by the software tool suite.